[16p-C302-1~18] 13.5 Semiconductor devices/ Interconnect/ Integration technologies

4:45 PM - 5:00 PM JST(7:45 AM - 8:00 AM UTC)

[16p-C302-13] Power-gating architecture and performance of nonvolatile SRAM

Taketo Kato¹, 〇Haruya Oki¹, Yusaku Shiotsu¹, Shuu'ichirou Yamamoto¹, Satoshi Sugahara¹ (1.FIRST, Tokyo Inst. of Tech.)

Keywords:

Power-gating,SRAM