[19p-A23-1~5] Advancements in Junction Technologies and Cutting-Edge Si-LSIs: Past, Present, and Future

1:30 PM - 2:15 PM JST(4:30 AM - 5:15 AM UTC)English Presentation

[19p-A23-1] Evolution of CMOS S/D Stressor Technology from Planar to 3-D Stacked Devices

〇John Ogawa Borland¹ (1.J.O.B. Technologies)

Keywords:

Selective Epitaxial Growth,S/D Stressor,Nanosheet devices

Today, use of Selective Epitaxial Growth (SEG) for CMOS Source Drain (S/D) stressor and Wrap Around Contacts (WAC) is standard FEOL processing for 3nm node FinFET and 2nm node Nanosheet devices. With improved contact resistance engineering, the SEG S/D structure is expected to continue to be used for 3-D stacked C-FET through at least the A3 technology node in 2034 as illustrated in Fig.1 [1]. This all started back in the 1980s when US and Japanese researchers investigated the use of SEG for elevated S/D and S/D contact filling. This talk will review the evolution of SEG S/D technology including the key recess etch p+ SiGe S/D structure for ultra shallow junction reported in the 1990s. This led to the production introduction of recess etched embedded-SiGe (eSiGe) PMOS S/D stressor to boost p-channel mobility by Intel at the 90nm node. However, the NMOS S/D stressor evolved from amorphous implantation at the 65nm node to eSiC SEG S/D stressor at 14/16nm 3-D FinFET. For one generation, the 32nm node, IBM/AMD/Samsung used PMOS channel-SiGe and NMOS eSiC S/D was used for IBM 22nm PD-SOI.

Fig.1: Intel CMOS stacked forksheet patent showing SEG-S/D warp-around contacts.

[1] C Huang et al., Intel US Patent on Stacked Forksheet Transistors, US 2021/0407999 A1, Dec 30, 2021.