Presentation Information
[7p-N301-12]Investigation of Degradation in FeFETs Using Quasi-Static Split C–V Techniques: Significant Trap Generation under Cycling Stress
〇Xuanhedong Gao1, Zuocheng Cai1, Zhenghong Liu1, Zhao Jin1, Xueyang Han1, Yan-kui Liang1, Yutong Chen1, Eishin Nako1, Shin-Yi Min1, Mitsuru Takenaka1, Shinichi Takagi1, Kasidit Toprasertpong1 (1.The Univ.of Tokyo)
Keywords:
Quasi-static split C-V,FeFET,Enduracne
Hafnia-based ferroelectric field-effect transistors (FeFETs) are compatible with conventional CMOS processes and are regarded as promising candidates for non-volatile memory applications owing to their fast access speed and scalability. However, silicon-based FeFETs suffer from poor endurance, primarily due to interface degradation and trap state generation. Recently, FeFETs employing oxide-semiconductor (OS) channels have demonstrated improved endurance characteristics and back-end-of-line (BEOL) compatibility toward monolithic 3D integration. Although many studies have reported robust memory windows (MW) and stable performance in OS FeFETs, the underlying mechanisms determining the difference in the endurance behaviors of FeFETs with Si and OS channels still need further investigation. Quasi-static split C-V (QSCV), also known as single-pulse charge pumping, has been widely adopted as a rapid characterization for trap state in various MOSFETs . In this study, QSCV techniques were applied to investigate endurance behaviors and trap generation in Si and OS FeFETs