[10p-A24-1~15] 11.4 Junction and circuit fabrication process, digital applications

4:30 PM - 4:45 PM JST(7:30 AM - 7:45 AM UTC)

[10p-A24-10] Delay time investigation of a Superconductive Random Number Generator with Acceleration Mechanism

〇Yoshinobu Tomitaka¹, Nobuyuki Yoshikawa^2,3,4, Yuki Yamanashi^2,3,4 (1.YNU Grad. Sch. Eng. Sci., 2.YNU Fac. Eng., 3.YNU IAS, 4.YNU IMS)

Keywords:

Random Number Generator

A high-speed SRNG, which incorporates a speed-enhancement mechanism into a superconducting random number generator (SRNG), has achieved a reduction in latency of more than 50% and is expected to be adopted in application circuits. To demonstrate the superiority of this high-speed SRNG in terms of latency, we designed a test circuit that compares the latency of the high-speed SRNG with that of an existing SRNG using delay flip-flops, and conduct a verification test.