[10p-S1-1~20] 13.5 Semiconductor devices/ Interconnect/ Integration technologies

5:00 PM - 5:15 PM JST(8:00 AM - 8:15 AM UTC)Presentation by Applicant for JSAP Young Scientists Presentation AwardEnglish Presentation

[10p-S1-13] GeOI Heterogeneous Integration and Device Fabrication Based on Wafer Bonding Technology

〇(D)Xiaofeng Duan^1,2,3, Shaoteng Wu^1,3, Mengnan Ke², Junwei Luo^1,3 (1.Inst. of Semiconductors, CAS, 2.Yokohama National Univ., 3.Univ. of CAS)

Keywords:

Direct Wafer Bonding,Defect Reduction,Ge pMOSFET

Germanium-on-insulator (GeOI) is a promising platform for future CMOS and photonic integration due to its high carrier mobility and compatibility with Si technology. In this work, a wafer-scale GeOI fabrication process based on direct wafer bonding was developed. Chemical wet activation and O₂ plasma activation were employed to improve surface hydrophilicity and bonding quality, resulting in a 6-inch GeOI wafer with an effective bonding area of approximately 96%. A post-bonding defect reduction process combining O₂ annealing and dilute HF treatment was further introduced, reducing the dislocation density by about two orders of magnitude. To evaluate the device applicability of the fabricated substrates, planar Ge pMOSFETs were fabricated using ozone oxidation gate-stack technology, exhibiting an on/off ratio of 1.64×10⁴ and a minimum subthreshold swing of 187 mV. These results demonstrate the feasibility of direct-bonded GeOI as a promising platform for future Ge-based CMOS and photonic applications.