[11a-S1-1~9] 13.5 Semiconductor devices/ Interconnect/ Integration technologies

9:15 AM - 9:30 AM JST(12:15 AM - 12:30 AM UTC)English Presentation

[11a-S1-2] Interconnect-Aware Design-Technology Co-Optimization of CFET-Based 6T SRAM for Advanced Logic Nodes

〇(D)Yaoping Xiao¹, Yuxuan Wang¹, Jinhyun Chun¹, Masaharu Kobayashi¹ (1.IIS, The Univ. of Tokyo)

Keywords:

CFET,SRAM,DTCO

Complementary field-effect transistors (CFETs) enable continued SRAM scaling beyond the 1-nm technology node through vertically stacked nMOS/pMOS integration. However, the required tall vias (TVs) introduce significant parasitic resistance and capacitance, limiting SRAM power, performance, and area (PPA). This work presents an interconnect-aware design-technology co-optimization (DTCO) for CFET-based 6T SRAM by jointly optimizing the frontside/backside interconnect architecture and cell layout. A three-dimensional CFET SRAM structure is developed, and parasitic RC extraction with SPICE simulations is performed to evaluate the proposed design. The optimized FS_VSS&BS_WL structure effectively reduces critical parasitic capacitances and improves terminal-dependent resistance, demonstrating the potential of interconnect-aware DTCO for high-performance and energy-efficient CFET SRAM at advanced logic nodes.