[11a-S1-1~9] 13.5 Semiconductor devices/ Interconnect/ Integration technologies | The 87th JSAP Autumn Meeting 2026

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Oral presentation13 Semiconductors : 13.5 Semiconductor devices/ Interconnect/ Integration technologies

[11a-S1-1~9]13.5 Semiconductor devices/ Interconnect/ Integration technologies

Fri. Sep 11, 2026 9:00 AM - 11:15 AM JST
Fri. Sep 11, 2026 12:00 AM - 2:15 AM UTC

S1 (First Year Education S Bldg.)

9:00 AM - 9:15 AM JST(12:00 AM - 12:15 AM UTC)English Presentation

[11a-S1-1]Study on Self-Heating and Reliability Impact in Self-Aligned Backside-Contact Complementary FET Device Structure

〇JINHYUN CHUN¹, Yuxuan Wang¹, Yaoping Xiao¹, Kobayashi Masaharu¹ (1.IIS, The Univ. of Tokyo)

9:15 AM - 9:30 AM JST(12:15 AM - 12:30 AM UTC)English Presentation

[11a-S1-2]Interconnect-Aware Design-Technology Co-Optimization of CFET-Based 6T SRAM for Advanced Logic Nodes

〇(D)Yaoping Xiao¹, Yuxuan Wang¹, Jinhyun Chun¹, Masaharu Kobayashi¹ (1.IIS, The Univ. of Tokyo)

9:30 AM - 9:45 AM JST(12:30 AM - 12:45 AM UTC)English Presentation

[11a-S1-3]Standard-Cell-Library Level PPA Evaluation of Monolithic Complementary FET with BM0-signal and M0-power Routing

〇(D)Yuxuan Wang¹, Yaoping Xiao¹, Jinhyun Chun¹, Masaharu Kobayashi¹ (1.The University of Tokyo)

9:45 AM - 10:00 AM JST(12:45 AM - 1:00 AM UTC)

[11a-S1-4]A new 3T gain cell and its application to pseudo-SRAM

〇Yusaku Shiotsu¹, Sei Yoshida¹, Chikahide Ichikawa¹, Satoshi Sugahara¹ (1.FIRST, Inst. of Sci. Tokyo)

10:00 AM - 10:15 AM JST(1:00 AM - 1:15 AM UTC)

[11a-S1-5]An asymmetric SRAM cell for EMP operation and its 16-parallel-READ-access macro application

〇Ryo Fujishita¹, Yusaku Shiotsu¹, Satoshi Sugahara¹ (1.FIRST, Inst. of Sci. Tokyo)

10:15 AM - 10:30 AM JST(1:15 AM - 1:30 AM UTC)

[11a-S1-6]Design of an EMP-SRAM cell for 0.275V operation and its application to an eight-parallel READ-access macro

〇Tomonori Mori¹, Yusaku Shiotsu¹, Satoshi Sugahara¹ (1.FIRST, Inst. of Sci. Tokyo)

10:30 AM - 10:45 AM JST(1:30 AM - 1:45 AM UTC)

[11a-S1-7]Near-EMP 32-parallel-processing in-memory BNN accelerator macro using 6T-based IRP cells

〇Hideto Yukita¹, Tadakatsu Yaguchi¹, Yusaku Shiotsu¹, Satoshi Sugahara¹ (1.FIRST, Inst. of Sci. Tokyo)

10:45 AM - 11:00 AM JST(1:45 AM - 2:00 AM UTC)English Presentation

[11a-S1-8]Flexible Complementary Analog and Digital Circuits Using Organic–Inorganic Hybrid Thin-Film Semiconductors

〇(D)Haonan Fan⁴, Tsurumi Junto¹, Makita Tatsuyuki¹, Tanaka Yuki¹, Kameyama Ryohei⁴, Yamashita Yu^3,4, Watanabe Shun⁴, Takeya Jun^1,2,3,4 (1.PI CRYSTAL., 2.JST CREST, 3.NIMS, 4.Univ. of Tokyo)

11:00 AM - 11:15 AM JST(2:00 AM - 2:15 AM UTC)

[11a-S1-9]Cubic-based integrated-circuit architectural design for three-dimensional logic LSIs

〇(B)Ginga Uchida¹, Zhenhao Wang¹, Peilong Wang¹, Shinya Imai¹, Satoshi Ueno², Atsushi Hori², Hitoshi Wakabayashi² (1.Science Tokyo, 2.Green-niX)

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