[11a-S1-1~9] 13.5 Semiconductor devices/ Interconnect/ Integration technologies

9:30 AM - 9:45 AM JST(12:30 AM - 12:45 AM UTC)English Presentation

[11a-S1-3] Standard-Cell-Library Level PPA Evaluation of Monolithic Complementary FET with BM0-signal and M0-power Routing

〇(D)Yuxuan Wang¹, Yaoping Xiao¹, Jinhyun Chun¹, Masaharu Kobayashi¹ (1.The University of Tokyo)

Keywords:

Complementary FET,Design-Technology Co-Optimization,Power-Performance-Area

In this work, we systematically evaluate three architectures of monolithic CFET at standard-cell-library level using design-technology co-optimization (DTCO) framework. The evaluation results show that the self-aligned backside contact (SABC) CFET with BM0-signal and M0-power routing provides better PPA for most cells.