[11a-S1-1~9] 13.5 Semiconductor devices/ Interconnect/ Integration technologies

10:15 AM - 10:30 AM JST(1:15 AM - 1:30 AM UTC)

[11a-S1-6] Design of an EMP-SRAM cell for 0.275V operation and its application to an eight-parallel READ-access macro

〇Tomonori Mori¹, Yusaku Shiotsu¹, Satoshi Sugahara¹ (1.FIRST, Inst. of Sci. Tokyo)

Keywords:

SRAM,Energy minimum point operation,Parallel-READ-access macro