[11a-S1-1~9] 13.5 Semiconductor devices/ Interconnect/ Integration technologies

10:30 AM - 10:45 AM JST(1:30 AM - 1:45 AM UTC)

[11a-S1-7] Near-EMP 32-parallel-processing in-memory BNN accelerator macro using 6T-based IRP cells

〇Hideto Yukita¹, Tadakatsu Yaguchi¹, Yusaku Shiotsu¹, Satoshi Sugahara¹ (1.FIRST, Inst. of Sci. Tokyo)

Keywords:

Neural network accelerator,Near-energy-minimum-point operation,Processing-in-memory