Presentation Information
[11p-N304-9]Application of the Agile-X Platform to Mega-Scale LSI Development Based on a Unified Yield-Reliability Model and EDA Feedback
〇Hirofumi Sumi1, Atsutake Kosuge1, Hideharu Amano1, Naonobu Shimamoto1, Yukinori Ochiai1, Shinji Tsuboi1, Tohru Mogami1, Yoshio Mita1, Makoto Ikeda1 (1.Systems Design Lab., UTokyo)
Keywords:
Agile-X Platform,Unified Yield-Reliability Model,EDA Feedback
This paper applies the Agile-X platform and Minimal Fab to mega-scale LSI development. A unified yield-reliability model integrates functional and parametric yields with reliability. It demonstrates that in mega-scale integration, statistical averaging makes functional yield dominant, strictly requiring a single-via defect rate under 100 ppb.
To maximize performance, an on-chip evaluation method is proposed. It analytically separates back-end-of-line (BEOL) wiring variation from front-end-of-line (FEOL) transistor variation by comparing delay differences in test circuits. Feeding this isolated BEOL variation into EDA tools minimizes prediction uncertainties. Integrating this feedback loop with established 200mm wafer processing techniques eliminates discrepancies between simulation and actual operation. This methodology improves turnaround time and design quality, establishing a foundation for democratizing semiconductor design.
To maximize performance, an on-chip evaluation method is proposed. It analytically separates back-end-of-line (BEOL) wiring variation from front-end-of-line (FEOL) transistor variation by comparing delay differences in test circuits. Feeding this isolated BEOL variation into EDA tools minimizes prediction uncertainties. Integrating this feedback loop with established 200mm wafer processing techniques eliminates discrepancies between simulation and actual operation. This methodology improves turnaround time and design quality, establishing a foundation for democratizing semiconductor design.