[WD3] Integrated Photonic Circuits and Platforms III

2:30 PM - 3:00 PM JST(5:30 AM - 6:00 AM UTC)Invited

[WD3-2] Integrated Testing Strategy of Wafer and Chip-level Characterization for Photonic Integrated Circuits

○Moataz Eissa¹, Tsuyoshi Horikawa¹, Suguru Yoshida¹, Nobuhiko Nishiyama^1,2,3 (1. Electrical and Electronic Engineering Department, Institute of Science Tokyo (Japan), 2. Institute of Integrated Research (IIR), Institute of Science Tokyo (Japan), 3. Photonics Electronics Technology Research Association (PETRA) (Japan))

We demonstrate wafer-level characterization of both passive silicon photonic integrated circuits and heterogeneously integrated III-V membrane DFB lasers on silicon. Strong agreement with chip-level results enables efficient screening tests for heterogeneous photonic integration.