Presentation Information

[WD3-2]Integrated Testing Strategy of Wafer and Chip-level Characterization for Photonic Integrated Circuits

○Moataz Eissa1, Tsuyoshi Horikawa1, Suguru Yoshida1, Nobuhiko Nishiyama1,2 (1Institute of Science Tokyo, 2Photonics Electronics Technology Research Association)
We demonstrate wafer-level characterization of both passive silicon photonic integrated circuits and heterogeneously integrated III-V membrane DFB lasers on silicon. Strong agreement with chip-level results enables efficient screening tests for heterogeneous photonic integration.