Session Details
[WD3]Integrated Photonic Circuits and Platforms III
Wed. Jul 2, 2025 2:00 PM - 4:00 PM JST
Wed. Jul 2, 2025 5:00 AM - 7:00 AM UTC
Wed. Jul 2, 2025 5:00 AM - 7:00 AM UTC
Room D (1F 107+108)
[WD3-1]Reliability Challenges for the Next Generation of Optical Communication Devices
○William Fegadolli1 (1. Nokia (United States of America))
[WD3-2]Integrated Testing Strategy of Wafer and Chip-level Characterization for Photonic Integrated Circuits
○Moataz Eissa1, Tsuyoshi Horikawa1, Suguru Yoshida1, Nobuhiko Nishiyama1,2,3 (1. Electrical and Electronic Engineering Department, Institute of Science Tokyo (Japan), 2. Institute of Integrated Research (IIR), Institute of Science Tokyo (Japan), 3. Photonics Electronics Technology Research Association (PETRA) (Japan))
[WD3-3]Wafer-scale Platform of PLZT on SiO2/Si Substrate toward Realizing High-Speed Optical Modulation
○Tomohiro Otani1, Sohei Nonaka1, Shiyoshi Yokoyama2 (1. Innovation Center, Mitsubishi Materials Corporation (Japan), 2. Institute for Materials Chemistry and Engineering, Kyushu University (Japan))
[WD3-4]Proposal of nano-pixel waveguide using photonic-crystal quasi-side-wall
Junliang Guo1, ○Haisong Jiang1, Kiichi Hamamoto1 (1. Kyushu university (Japan))
[WD3-5]A Reconfigurable-Resolution OADC based on Programmable Photonic Integrated Circuits with Automatic Defect-Tolerant Configuration
○Ran Tao1, Jifang Qiu1, Bowen Zhang1, Jian Wu (1. Beijing University of Posts and Telecommunications (China))
[WD3-6]Diffraction Engineering Enabled by Bound States in the Continuum in Evanescent Field
○Weiming Yao1,2,3,4, Wanchang Gao1,2,3,4, Yang Feng1,2,3,4, Yanmei Li1,2,3,4, Jiewen Li1,2,3,4, Jinzhao Wang1,2,3,4, Rui Li1,2,3,4, Xiaochuan Xu1,2,3,4 (1. National Key Laboratory of Laser Spatial Information (China), 2. Guangdong Provincial Key Laboratory of Integrated Photonic-Electronic Chip (China), 3. Guangdong Provincial Key Laboratory of Aerospace Communication and Networking Technology (China), 4. Harbin Institute of Technology, Shenzhen (China))