[Session 1] Session 1: Memory Devices

2:30 PM - 2:50 PM JST(5:30 AM - 5:50 AM UTC)

[Session_1-05] Enabling 4F² DRAM Junctionless Vertical Channel Transistors with Novel Oxygen Inserted Si Substrates – A TCAD Study

*Albert Lu¹, Madhav Raj², Hiu Yung Wong², Ilya Rumyantsev¹, Shuyi Li¹, Hideki Takeuchi¹ (1. Atomera Inc., 2. San Jose State Univ.)