SISPAD2026
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Session Details

OralSession 1: Memory

[Session 1]Session 1: Memory Devices

Mon. Sep 28, 2026 1:00 PM - 2:50 PM JST
Mon. Sep 28, 2026 4:00 AM - 5:50 AM UTC
Room A1(3rd floor)
1:00 PM - 1:30 PM JST(4:00 AM - 4:30 AM UTC)

[Session_1-01]From Device Physics to Circuit Co-Design: Multi-Physics Modeling of Monolithic 3D CMOS-NEM Hybrid Circuits

*Woo Young Choi1 (1. Seoul National University)
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1:30 PM - 1:50 PM JST(4:30 AM - 4:50 AM UTC)

[Session_1-02]Simulation Study on Scaling Limits of Z-direction Pitch in 3D Flash Memories: Toward the Sub-40 nm Regime

*Tatsuo Ogura1, Yuma Hizume1, Yuto Ozeki1, Takayuki Kakegawa1, Hiroshi Takeda1, Takashi Kurusu1, Tomohiro Oki1, Katsuyuki Sekine1 (1. KIOXIA Corp.)
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1:50 PM - 2:10 PM JST(4:50 AM - 5:10 AM UTC)

[Session_1-03]Vertical Channel-All-Around a-IGZO-FET Towards 2T1D eDRAM Design with Self-Boosted Storage-Node Voltage

*Wenxiang Tang1,2, Xufan Li1,2, Yue Zhao1,2, Xiaoyi Zhang1,2, Qingxiao Zhu1,2, Jingrui Guo3, Lingfei Wang1,2, Ling Li1,2 (1. State Key Lab of Fabrication Technologies for Integrated Circuits, Institute of Microelectronics, Chinese Academy of Sciences, 2. University of Chinese Academy of Sciences, 3. School of Information Science and Engineering, Shandong University)
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2:10 PM - 2:30 PM JST(5:10 AM - 5:30 AM UTC)

[Session_1-04]Compact Modeling of the Program Saturation Regime in
Charge Trap Flash Memories

*Thomas Hellemans1,2, Devin Verreck1,2, Antonio Arreghini1, Geert Van den bosch1, Maarten Rosmeulen1,2, Michel Houssa2,1, Jan Van Houdt1,2 (1. Imec, 2. KU Leuven)
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2:30 PM - 2:50 PM JST(5:30 AM - 5:50 AM UTC)

[Session_1-05]Enabling 4F2 DRAM Junctionless Vertical Channel Transistors with Novel Oxygen Inserted Si Substrates – A TCAD Study

*Albert Lu1, Madhav Raj2, Hiu Yung Wong2, Ilya Rumyantsev1, Shuyi Li1, Hideki Takeuchi1 (1. Atomera Inc., 2. San Jose State Univ.)
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