[Session 4] Session 4: Numerical Methods and Algorithms

3:30 PM - 3:50 PM JST(6:30 AM - 6:50 AM UTC)

[Session_4-01] Efficient Simulation of Gate Leakage Currents in Ultra-scaled Transistors from First Principles

*Mauro Dossena¹, Nicolas Vetsch¹, Alexander Maeder¹, Anders Winka¹, Vincent Maillou¹, Denghui Lu¹, Alexandros Nikolaos Ziogas¹, Jiang Cao¹, Mathieu Luisier¹ (1. Integrated System Laboratory (IIS), ETH Zürich, Switzerland)