[Session 6] Session 6: Process Simulation

9:50 AM - 10:10 AM JST(12:50 AM - 1:10 AM UTC)

[Session_6-02] A First-Principles Study of F₂ Selective Etching of Si/SiGe Stacks towards Sub-3 nm Node Transistor Manufacturing

*Qikai Zhao^1,2, Junjie Li¹, Hua Shao¹, Rui Chen¹, Lado Filipovic³ (1. State Key Lab. of Fabrication Technologies for Integrated Circuits, Institute of Microelectronics, Chinese Academy of Sciences, 2. School of Integrated Circuits, Univ. of Chinese Academy of Sciences, 3. CDL for Multi-Scale Process Modeling of Semiconductor Devices and Sensors, Institute for Microelectronics, TU Wienna)