SISPAD2026
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Session Details

OralSession 6: Process

[Session 6]Session 6: Process Simulation

Tue. Sep 29, 2026 9:30 AM - 11:30 AM JST
Tue. Sep 29, 2026 12:30 AM - 2:30 AM UTC
Room A2(3rd floor)
9:30 AM - 9:50 AM JST(12:30 AM - 12:50 AM UTC)

[Session_6-01]Unified Lattice Kinetic Monte Carlo Model for Epitaxy, Etch and Reflow Processes for Advanced Semiconductor Device Architectures

*Alexander Schmidt1, Kyungmi Yeom1, Byounghak Lee2, Marton Voeroes2, Hiroyuki Kubotera2, Woosung Choi2, Anthony Payet3, Takeshi Nishimatsu3, Hiroo Koshimoto3, Joohyun Jeon1, Seungmin Lee1, Jaehoon Jeong1 (1. Samsung Electronics Co., Ltd, 2. Samsung Semiconductor Inc., 3. Samsung Device Solutions R&D Japan)
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9:50 AM - 10:10 AM JST(12:50 AM - 1:10 AM UTC)

[Session_6-02]A First-Principles Study of F2 Selective Etching of Si/SiGe Stacks towards Sub-3 nm Node Transistor Manufacturing

*Qikai Zhao1,2, Junjie Li1, Hua Shao1, Rui Chen1, Lado Filipovic3 (1. State Key Lab. of Fabrication Technologies for Integrated Circuits, Institute of Microelectronics, Chinese Academy of Sciences, 2. School of Integrated Circuits, Univ. of Chinese Academy of Sciences, 3. CDL for Multi-Scale Process Modeling of Semiconductor Devices and Sensors, Institute for Microelectronics, TU Wienna)
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10:10 AM - 10:30 AM JST(1:10 AM - 1:30 AM UTC)

Break

10:30 AM - 10:50 AM JST(1:30 AM - 1:50 AM UTC)

[Session_6-03]Geometry-Agnostic Feature-Scale PEALD Model

*Philipp Haslhofer1, Tobias Reiter1, Alexander Toifl2, Andreas Hössinger2, Lado Filipovic1 (1. Institute for Microelectronics, TU Wien, 2. Silvaco Europe Ltd., Silvaco Inc.)
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10:50 AM - 11:10 AM JST(1:50 AM - 2:10 AM UTC)

[Session_6-04]GPU-Accelerated Feature-Scale Process Simulation of CFET Structures

*Tobias Reiter1, Lado Filipovic1 (1. Institute for Microelectronics, TU Wien)
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11:10 AM - 11:30 AM JST(2:10 AM - 2:30 AM UTC)

[Session_6-05]Surrogate-Assisted Calibration of a DRIE Process Model

*Roman Kostal1, Manuel Kleinbichler3, Stefano Di Nicola4, Lado Filipovic1,2 (1. Inst. for Microelectronics, Tech. Univ. Vienna, 2. CDL for Multi-Scale Process Modeling of Semiconductor Devices and Sensors, 3. KAI Kompetenzzentrum Automobil- und Industrieelektronik GmbH, 4. Infineon Technologies Austria AG)
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