[2] Stacked Architecture and 3D Integration

10:10 AM - 10:30 AM JST(1:10 AM - 1:30 AM UTC)

[2-02] Optimizing CFET Parasitic Capacitance and Performance Through Middle Dielectric Isolation and Middle Via Integration

*Meng-Lin Wu¹, Yu-Cheng Lu¹, Vita Pi-Ho Hu¹ (1. National Taiwan University (Taiwan))