Presentation Information

[A-6-02]Efficitent FPGA Implementation of Multiple-Input Adders Using Generalized Parallel Counter (6,0,7;5)

Mugi Noda1, ◎Ryo Kanai1, Nagisa Ishiura1 (1. Kwansei Gakuin U)

Keywords:

FPGA,Multi-Input Adder,Generalized Parallel Counter