[A-6] VLSI設計技術

10:15 AM - 10:30 AM JST(1:15 AM - 1:30 AM UTC)Candidate for Academic Incentive Award

[A-6-02] Efficitent FPGA Implementation of Multiple-Input Adders Using Generalized Parallel Counter (6,0,7;5)

Mugi Noda¹, ◎Ryo Kanai¹, Nagisa Ishiura¹ (1. Kwansei Gakuin U)

Keywords:

FPGA,Multi-Input Adder,Generalized Parallel Counter