[A-19] Hardware Security

2:15 PM - 2:30 PM JST(5:15 AM - 5:30 AM UTC)

[A-19-03] Evaluation of SAT attack resistance in a Logic-Locking circuit using AES S-Box

〇Yuki Shimmura¹, Yuto Takino¹, Daiki Miyahara¹, Yang Li¹, Kazuo Sakiyama¹ (1. The University of Electro-Communications)

Keywords:

Logic Locking,SAT Attack,IP Protection,Integrated Circuit