[AS-1] State-of-the-art Chiplet Design Technologies

2:10 PM - 2:35 PM JST(5:10 AM - 5:35 AM UTC)

[AS-1-02] Efficient Wiring Layout for UCIe to Realize Low-cost and Chiplet-type Package Substrate

〇Soshi Shimomura¹, Yutaka Uematsu¹, Katusya Kikuchi¹, Haruo Shimamoto¹, Yuuki Araga¹, Shinichi Ouchi¹ (1. National Institute of Advanced Industrial and Science Technology)

Keywords:

Chiplet,UCIe,Wiring Layout,Signal Integrity,Organic Package