[AS-1] State-of-the-art Chiplet Design Technologies | IEICE Society Conference 2025

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公募シンポジウムセッションS. Public symposium session : AS-1．State-of-the-art Chiplet Design Technologies

[AS-1]State-of-the-art Chiplet Design Technologies

Wed. Sep 10, 2025 1:45 PM - 3:00 PM JST
Wed. Sep 10, 2025 4:45 AM - 6:00 AM UTC

Building for General Education (A/B/C) 3F A32(Okayama University)

Chair:Takashi Matsumoto

1:45 PM - 2:10 PM JST(4:45 AM - 5:10 AM UTC)

[AS-1-01]The Cutting Edge of 3D-IC and Chiplet Design: Accelerating Advanced Packaging with Cadence’s Integrated Solutions

〇Toru Makii¹ (1. Cadence Design Systems)

2:10 PM - 2:35 PM JST(5:10 AM - 5:35 AM UTC)

[AS-1-02]Efficient Wiring Layout for UCIe to Realize Low-cost and Chiplet-type Package Substrate

〇Soshi Shimomura¹, Yutaka Uematsu¹, Katusya Kikuchi¹, Haruo Shimamoto¹, Yuuki Araga¹, Shinichi Ouchi¹ (1. National Institute of Advanced Industrial and Science Technology)

2:35 PM - 3:00 PM JST(5:35 AM - 6:00 AM UTC)

[AS-1-03]AI chip Design Center Design Environment and Operation

〇Atsushi Hasegawa¹, Makoto Ikeda¹, Yasushi Igarashi², Ichiro Naka², Kunio Uchiyama² (1. The University of Tokyo, 2. National Institute of Advanced Industrial Science and Technology)

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