[AS-1] State-of-the-art Chiplet Design Technologies

2:35 PM - 3:00 PM JST(5:35 AM - 6:00 AM UTC)

[AS-1-03] AI chip Design Center Design Environment and Operation

〇Atsushi Hasegawa¹, Makoto Ikeda¹, Yasushi Igarashi², Ichiro Naka², Kunio Uchiyama² (1. The University of Tokyo, 2. National Institute of Advanced Industrial Science and Technology)

Keywords:

SoC Design,Design Platform