Presentation Information
[C-12-28]Efficiency Enhancement of a 24-GHz 180-nm CMOS Doherty Power Amplifier Using an Adaptive Bias Circuit
◎Kei Saito1, Kyoya Takano1 (1. Tokyo university of science)
Keywords:
CMOS,FR3,Doherty Amplifier,adaptive bias
ecently, communication systems after 5G use signals with a high peak-to-average power ratio (PAPR). Therefore, power amplifiers need high efficiency in the back-off region. The Doherty amplifier is a good solution because it keeps high efficiency over a wide input power range. It consists of a carrier amplifier and a peak amplifier. At low input power, only the carrier amplifier works, while at high input power both amplifiers work together. However, at 20 GHz, the gain of the Class-B or Class-C peak amplifier is low, which reduces the efficiency. The goal of this study is to develop an adaptive bias circuit that changes the peak amplifier from Class-B or Class-C to Class-A only at high input power. As the first step, a 20 GHz Doherty amplifier without the adaptive bias circuit was designed and fabricated using a 180 nm CMOS process. Driver stages were added to both amplifiers, and LCL matching networks were used for impedance matching. The effect of the gate bias of the peak amplifier on power-added efficiency (PAE) was evaluated. The measurement results showed that changing the gate bias according to the input power improved the PAE at high output power. These results show that adaptive control of the peak amplifier bias is an effective method for improving the efficiency of Doherty amplifiers.