Presentation Information
[C-12-36]Research on Circuit and Layout Generation of RISC-V Processor Using Agentic AI
〇Kanta Fukuda1, Wenqain Wang1, Haruto Tanaka1, Ned Sureechainirun1, Nabil Soliman1, Yuncheng Zhang1, Hiroyuki Sakai1, Kazuaki Kunihiro1, Kenichi Okada1 (1. Institute of Science Tokyo)
Keywords:
Digital Circuit,AI,Automation
While demand for custom processors is surging, the design process from RTL to physical layout requires highly specialized expertise. This study introduces autonomously operating "Agentic AI" to propose an end-to-end circuit and physical layout generation workflow without human intervention. Within this framework, the AI agent autonomously manages a digital design flow, iterating through circuit construction, functional verification, logic synthesis, place and route, and physical verification. Furthermore, it extracts parasitic components from the layout to perform post-layout simulations, automatically feeding back to the logic synthesis phase for re-optimization if any violations occur. To evaluate this workflow, a demonstration experiment was conducted using the open-source RISC-V core "Ibex" as a baseline. The AI agent successfully designed and integrated a flip-flop-based memory, an SPI controller, and a GPIO controller. Without any human designer intervention, the system achieved completely autonomous layout generation for the entire system, yielding a processor with a layout size of 605 µm × 605 µm and demonstrating the practicality of Agentic AI-driven automation.