Presentation Information
[N-2-07]Evaluation of an acceleration method of garbled circuits for optical secure computation
◎Mika Sekiguchi1, Yusuke Fujii1, Taiga Yahagi1, Tomoki Yamagami1, Atsushi Uchida1 (1. Saitama Univ.)
Keywords:
Secure computation,Information security,Garbled circuits
Secure computation enables multiple users to perform computations without revealing their private input data. One of the most widely used implementations of secure computation is the garbled circuit protocol. Garbled circuits conceal the computation by assigning random labels to the inputs and outputs of logic circuits; however, they require a large number of cryptographic operations, resulting in high computational cost. To improve the efficiency of garbled circuits, the Free XOR and half-gate techniques have been proposed. In this study, we implement the Free XOR and half-gate techniques as an acceleration method for garbled circuits toward the optical implementation of secure computation, and evaluate their effectiveness through numerical simulations. The Free XOR technique eliminates the need for ciphertext generation in XOR gates, while the half-gate technique reduces the number of ciphertexts required for AND gates and related logic gates, thereby decreasing the overall cryptographic cost. We evaluated the garbling and evaluation times by solving the 64-bit Millionaires' Problem. As a result, the proposed method reduced the garbling time by 62% and the evaluation time by 92% compared with the conventional method.