講演情報
[11a-PB3-1]An electrode design strategy to minimize ferroelectric imprint effect
〇(D)YUWEI CHEN1,6, DONGUUAN YU2, CHUNWEI HUANG3, YUNGCHI SU1, CHAORONG CHEN1, WEICHEN HUNG1, Bhagwati Prasad4, Ramamoorthy Ramesh5, YENLIN HUANG1 (1.Department of Materials Science and Engineering, National Yang Ming Chiao Tung University, 2.Taiwan Semiconductor Research Institute, 3.Department of Materials Science and Engineering, Feng Chia University, 4.Department of Materials Engineering, Indian Institute of Science, Bangalore, 5.Department of Materials Science and Engineering, University of California, Berkely, 6.Institute for Material Research, Tohoku University)
キーワード：
Ferroelectrics、Multiferroics、Electrode
Ferroelectric imprint, manifested as asymmetric polarization switching behavior, remains a critical challenge for the reliability and performance of ultra-low-voltage ferroelectric devices, including MagnetoElectric Spin-Orbit (MESO) devices, Ferroelectric Random-Access Memory (FeRAM), Ferroelectric Field-Effect Transistors (FeFETs), and Ferroelectric Tunnel Junctions (FTJs). In this work, we systematically investigate the impact of electrode configuration on the imprint behavior in different ferroelectric device architectures. By controlling the oxygen pressure during the deposition of La0.7Sr0.3MnO3 (LSMO) electrodes, the electrode work function can be effectively tuned, enabling precise modulation of the built-in voltage offset (Voffset) in ferroelectric capacitors. The results show that increasing the oxygen pressure enhances the work function of LSMO, thereby compensating for Voffset and improving polarization switching symmetry. Furthermore, a hybrid bottom electrode consisting of LSMO and SrRuO3 was developed to suppress the imprint effect. The optimized device exhibits a low coercive voltage of 0.3 V, a small Voffset of 0.06 V, excellent endurance exceeding 1E9 switching cycles, and stable polarization retention under zero-bias conditions. These results demonstrate an effective electrode-engineering strategy for mitigating ferroelectric imprint and improving device reliability. The proposed approach provides practical design guidelines for next-generation ultra-low-power ferroelectric electronics and offers a scalable route toward high-performance ferroelectric devices.