講演情報
[9a-S1-7]Surface Orientation Dependence of Interface Trap Density Reduction by Annealing in Si/SiO2 Interfaces
〇(D)Yutong Chen1, Ryotaro Shimura1, Koji Matsumoto2, Akihiro Suzuki2, Hiroaki Yamamoto2, Kazuto Matsukawa2, Mitsuru Takenaka1, Shinichi Takagi3, Kasidit Toprasertpong1 (1.Univ. Tokyo, 2.SUMCO, 3.Teikyo Univ.)
キーワード：
Si MOS capacitor、Interface state density、Post-metallization annealing
With the increasing adoption of multi-channel device architectures such as gate-all-around FETs, optimization of the Si/SiO2 interface for different surface orientations has become increasingly important. In this study, we investigated the effects of post-metallization annealing (PMA) temperature and annealing ambient on the interface state density (Dit) of Si MOS capacitors fabricated on (100), (110), (111), and (551) substrates. PMA was performed in forming gas (96% N2/4% H2) or pure N2 ambient at 300, 350, and 400 °C, and Dit was evaluated using the high–low C–V method. Dit was significantly reduced after PMA, and the improvement tended to saturate above 350 °C. The (110) orientation showed weaker Dit reduction than the (111) orientation, indicating surface-orientation dependence of PMA effectiveness. In contrast, FGA and N2 annealing showed similar trends, suggesting that PMA temperature and surface orientation are dominant factors.