[A-1] 回路とシステム

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[A-1-11] Method for Downsizing AES-Encryption Circuit on FPGA by Integrating Processing Modules

○Hiroyuki Fujii¹, Toshiyuki Inoue¹, Akira Tsuchiya¹, Kishine Keiji¹ (1. The Univ, of Shiga Pref.)

Keywords:

FPGA,Encrypt,AES