The Institute of Electronics, Information and Communication Engineers General Conference
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Presentation Information

11:30 AM - 11:45 AM JST(2:30 AM - 2:45 AM UTC)

[C-12-32]A Fully Synthesizable DPLL for Spread Spectrum Clock Generation

○Waleed Madany1, Huang Hongye 1, Liu Bangan 1, Shirane Atsushi 1, Okada Kenichi1 (1. Tokyo Institute of Technology)
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Keywords:

Fully Synthesizable,DPLL

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