[C-12] Integrated Circuit and Devices

2:45 PM - 3:00 PM JST(5:45 AM - 6:00 AM UTC)Candidate for Academic Incentive Award

[C-12-05] Hierarchical Bit-Line Sensing Scheme for Advanced 3D NAND Flash

◎MAO FONG LUO¹, Toru Tanzawa¹ (1. Graduate School of Infomation, Production and Systems, Waseda University)

Keywords:

NAND Flash,Sense Scheme,low-power design,BL path,Delays