[C-12] 集積回路

14:45 〜 15:00学術奨励賞候補対象

[C-12-05] Hierarchical Bit-Line Sensing Scheme for Advanced 3D NAND Flash

◎MAO FONG LUO¹, Toru Tanzawa¹ (1. Graduate School of Infomation, Production and Systems, Waseda University)

キーワード：

NAND Flash、Sense Scheme、low-power design、BL path、Delays

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