[G] Solid process/ Solid and welding process(1):Soldering(1)

3:05 PM - 3:20 PM JST(6:05 AM - 6:20 AM UTC)

[314] Delamination Analysis of Dielectric Film / Redistribution Materials Interface in Large – Scale Semiconductor Packaging Structure

*Daisuke ANDO¹, Yoshiharu KARIYA² (1. Graduate School of Shibaura Institute of Technology, 2. College of Engineering, Shibaura Institute of Technology)

Keywords:

Large – Scale Semiconductor Package,Dielectric film,Finite Element Method,Cohesive Zone Model,Critical energy release rate

大規模半導体実装構造を模擬した2次元FEMモデルを作製し，応力解析をした結果，中間層のSi / モールド界面近傍の再配線層に応力が集中し，絶縁膜 / 配線材料界面に剥離が発生する可能性があった.