[20a-A304-1~11] 13.5 Semiconductor devices/ Interconnect/ Integration technologies

11:30 AM - 11:45 AM JST(2:30 AM - 2:45 AM UTC)

[20a-A304-10] Design and analysis of an 8kB macro for a new ultralow-voltage retention SRAM

〇Katsutoshi Ito¹, Yusaku Shiotsu¹, Satoshi Sugahara¹ (1.FIRST, Tokyo Inst. of Tech.)

Keywords:

power gating,SRAM