The 84th JSAP Autumn Meeting 2023
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Oral presentation13 Semiconductors : 13.5 Semiconductor devices/ Interconnect/ Integration technologies

[20a-A304-1~11]13.5 Semiconductor devices/ Interconnect/ Integration technologies

Wed. Sep 20, 2023 9:00 AM - 12:00 PM JST
Wed. Sep 20, 2023 12:00 AM - 3:00 AM UTC
A304 (KJ Hall)
Wen Hsin Chang(AIST)
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9:00 AM - 9:15 AM JST(12:00 AM - 12:15 AM UTC)

[20a-A304-1]Additional High-Pressure Hydrogen Annealing Improving the Cryogenic Operation of Si (110)-oriented n-MOSFETs

〇(D)Shunsuke Shitakata1,2, Hiroshi Oka1, Takumi Inaba1, Shota Iizuka1, Kimihiko Kato1, Takahiro Mori1 (1.AIST, 2.APPI, Keio)
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9:15 AM - 9:30 AM JST(12:15 AM - 12:30 AM UTC)

[20a-A304-2]Condition to overestimate DIBL parameter in cryogenic operation of MOSFETs

〇(M1)Yuika Kobayashi1,2, Hidehiro Asai2, Shota Iizuka2, Junichi Hattori2, Tsutomu Ikegami2, Koichi Fukuda2, Tetsuro Nikuni1, Takahiro Mori2 (1.Tokyo Univ. of Science, 2.AIST)
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9:30 AM - 9:45 AM JST(12:30 AM - 12:45 AM UTC)

[20a-A304-3]Verification of a New Charge-Based Threshold Voltage Definition

〇KIYOSHI TAKEUCHI1, MASAHARU KOBAYASHI2,1, TOSHIRO HIRAMOTO1 (1.IIS, Univ. Tokyo, 2.d.lab, Univ. Tokyo)
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9:45 AM - 10:00 AM JST(12:45 AM - 1:00 AM UTC)

[20a-A304-4]Effects of quantum confinement on electron velocity overshoot in Si nanosheet FETs

〇Junichi Hattori1, Koichi Fukuda1, Tsutomu Ikegami1, Yoshihiro Hayashi1 (1.AIST)
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10:00 AM - 10:15 AM JST(1:00 AM - 1:15 AM UTC)

[20a-A304-5]Integrate-and-Fire Operation by using “Dual-Gate PN-Body Tied SOI-FET”

〇(M2)Haruki Yonezaki1, Takayuki Mori1, Jiro Ida1 (1.Kanazawa Inst. of Tech.)
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10:30 AM - 10:45 AM JST(1:30 AM - 1:45 AM UTC)

[20a-A304-6]Threshold Voltage Control by Al Diffusion for NMOSFET with Metal Gate Stack

〇Yuya Omura1, Shoji Aota1, Tomoya Wada1, Tomoyuki Funabasama1, Kasumi Yasuda1, Daisuke Watanabe1, Hiroki Okamoto1, Isamu Ito1, Masato Koyama1 (1.KIOXIA)
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10:45 AM - 11:00 AM JST(1:45 AM - 2:00 AM UTC)

[20a-A304-7]Improvement of current drivability for metal S/D Ge n-MOSFET by introduction of recessed channel structure (III)

〇Hajime Kuwazuru1, Dong Wang2, Keisuke Yamamoto2 (1.IGSES, Kyushu Univ., 2.FES, Kyushu Univ.)
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11:00 AM - 11:15 AM JST(2:00 AM - 2:15 AM UTC)English Presentation

[20a-A304-8]Performance Enhancement of Extremely-thin Body (111) Ge-on-Insulator nMOSFETs by Using Flipped Substrate Process

〇Xueyang Han1, Chia-Tsong Chen1, Kei Sumita1, Kasidit Toprasertpong1, Mitsuru Takenaka1, Shinichi Takagi1 (1.Univ. Tokyo)
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11:15 AM - 11:30 AM JST(2:15 AM - 2:30 AM UTC)Presentation by Applicant for JSAP Young Scientists Presentation Award

[20a-A304-9]A Nanosheet Oxide Semiconductor FET Using ALD InGaOx Channel for 3D Integrated Devices

〇Kaito Hikake1, Zhuo Li1, Junxiang Hao1, Chitra Pandy1, Takuya Saraya1, Toshiro Hiramoto1, Takanori Takahashi2, Mutsunori Uenuma2, Yukiharu Uraoka2, Masaharu Kobayashi1,3 (1.IIS, Univ. of Tokyo, 2.NAIST, 3.d.lab, Univ. of Tokyo)
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11:30 AM - 11:45 AM JST(2:30 AM - 2:45 AM UTC)

[20a-A304-10]Design and analysis of an 8kB macro for a new ultralow-voltage retention SRAM

〇Katsutoshi Ito1, Yusaku Shiotsu1, Satoshi Sugahara1 (1.FIRST, Tokyo Inst. of Tech.)
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11:45 AM - 12:00 PM JST(2:45 AM - 3:00 AM UTC)

[20a-A304-11]A binarized neural network accelerator macro with parallelized MAC units using ULVR-SRAM

〇Yusaku Shiotsu1, Satoshi Sugahara1 (1.FIRST, Tokyo Inst. of Tech.)
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