[20a-A304-1~11] 13.5 Semiconductor devices/ Interconnect/ Integration technologies

11:45 AM - 12:00 PM JST(2:45 AM - 3:00 AM UTC)

[20a-A304-11] A binarized neural network accelerator macro with parallelized MAC units using ULVR-SRAM

〇Yusaku Shiotsu¹, Satoshi Sugahara¹ (1.FIRST, Tokyo Inst. of Tech.)

Keywords:

Binarized neural network accelerator,Energy minimum-point operation,processing-in-memory