[18a-A23-1~13] 13.5 Semiconductor devices/ Interconnect/ Integration technologies

9:15 AM - 9:30 AM JST(12:15 AM - 12:30 AM UTC)

[18a-A23-2] Negative Back Bias Effect of Cryogenic 200 nm SOI MOSFET

〇Ryusei Ri¹, Takayuki Mori¹, Kousuke Hatta¹, Ryousuke Kobayashi¹, Hiroshi Oka², Takahiro Mori², Jiro Ida¹ (1.Kanazawa Univ., 2.AIST)

Keywords:

Cryo-CMOS,SOI MOSFET,Back bias

In order to increase the number of qubits in a quantum computer, the increase in the number of wirings and the heat inflow from them is an issue, and research and development of Cryo-CMOS technology has been conducted to solve this problem. Among MOSFETs, SOI technology can control the threshold voltage (Vth) by the substrate bias (Vsub), and is expected to realize low-power Cryo-CMOS. In this paper, we report on the temperature dependence of the negative substrate bias, which is the direction in which Vth is raised, and show different behaviors at low and room temperatures.