[19p-B1-1~16] 13.3 Insulator technology

3:30 PM - 3:45 PM JST(6:30 AM - 6:45 AM UTC)Presentation by Applicant for JSAP Young Scientists Presentation Award

[19p-B1-10] Low temperature (210 °C) fabrication of Ge gate stack and its interfacial dipole analysis

〇Hajime Kuwazuru¹, Taisei Aso¹, Dong Wang², Keisuke Yamamoto² (1.IGSES, Kyushu Univ., 2.FES, Kyushu Univ.)

Keywords:

Germanium,Gate stack,Low-temperature process

Ge is a strong candidate material for novel electronic devices such as spin MOSFET or 3D-LSI. A high-quality insulator on Ge should be formed at low temperature to realize these applications. We fabricated a Ge MOS capacitor (CAP) and n-MOSFET with a SiO₂/GeO₂ gate dielectric at a low temperature of 210 °C. The MOSCAP and n-MOSFET show the typical electrical characteristics without significant degradation compared with the samples fabricated at a higher temperature of 450 °C. On the other hand, we confirmed flatband voltage (V_FB) significantly shifted to a positive direction. From the V_FB comparison among different annealing temperatures, high-temperature annealing induces the interface dipole formation in the gate insulator, that significantly shift V_FB to a negative direction. XPS analysis suggests the origin of interface dipole is oxygen atom movement at a SiO₂/GeO₂ interface. This information will be an important guideline for fabricating a high-quality insulator on Ge at low temperature.