[25p-31A-1~9] FS.1 Focused Session "AI Electronics"

2:00 PM - 2:15 PM JST(5:00 AM - 5:15 AM UTC)

[25p-31A-4] Performance improvement of FeFET reservoir computing by parallelization of FeFETs with delayed input to the substrate terminal

〇Eishin Nako¹, Kasidit Toprasertpong¹, Ryosho Nakane¹, Rikuo Suzuki¹, Mitsuru Takenaka¹, Shinichi Takagi¹ (1.Univ. Tokyo)

Keywords:

reservoir computing,FeFET

In physical reservoir computing, short-term memory characteristics and nonlinearity are considered necessary for achieving high performance. We have focused on the short-term memory characteristics and nonlinearity of ferroelectric gate MOSFETs (FeFETs) and have experimentally demonstrated FeFET reservoir computing. We succeeded in improving the reservoir performance of a single device by applying a delayed input to the substrate terminal in addition to the input to the gate terminal of the FeFET. In this study, by preparing multiple FeFETs and varying the delay time of the pulses input to the substrate for each FeFET, we achieved further improvement in reservoir computing performance through parallelization.