[10p-N302-1~11] 13.5 Semiconductor devices/ Interconnect/ Integration technologies

2:15 PM - 2:30 PM JST(5:15 AM - 5:30 AM UTC)

[10p-N302-4] A parallel-processing-in-memory BNN accelerator macro using XNOR-SRAM

〇Kein Kondo¹, Yusaku Shiotsu¹, Satoshi Sugahara¹ (1.FIRST, Inst. of Sci. Tokyo)

Keywords:

SRAM,energy minimum-point operation,processing-in-memory