Presentation Information
[8a-N324-2]Development and Contact Resistance Evaluation of Two-Layer Al Interconnection for AIHardware using Minimal Fab
〇Hirofumi Sumi1, Naonobu Shimamoto1, Yukinori Ochiai1, Tohru Mogami1, Yoshio Mita1, Makoto Ikeda1 (1.The Univ. of Tokyo, Systems design lab.)
Keywords:
minimal fab,CMOS Process,two-layer interconnection
The rapid evolution of AI algorithms necessitates high-performance hardware, especially in Very Large Scale Integration (VLSI). As circuit dimensions decrease, via contact resistance emerges as a critical determinant of device speed and reliability. This research addresses the demand for cost-effective and rapid AI hardware LSI development by introducing a two-layer aluminum (Al) multilevel interconnect technology fabricated in a minimal-fab environment. Our process entailed depositing a 350nm SiO2 interlevel dielectric (ILD) on 0.5-inch silicon wafers, followed by sputtering Ti/Al-Si1%/TiN stacks for both metal layers. Maskless exposure and dry etching precisely defined the interconnect patterns and via holes. To optimize contact resistance, reverse sputter cleaning preceded the deposition of the second metal layer. The achieved 2µm wide interconnects and minimum 2µm spacing underscore the process's precision. Evaluation of contact resistance yielded promising results. Via chain measurements indicated approximately 1ohm per via, while Kelvin four-terminal measurements recorded 35.8 mΩ for 2µm vias and 7.45 mΩ for 3µm vias. Although these values exceed theoretical predictions (e.g., 2.95 mΩ for a 2µm via), likely attributable to incomplete Al-Si1% filling and interface resistance, they remain practically acceptable for AI hardware LSI gate array wiring. This study validates the efficacy of minimal fabs for agile, cost-effective prototyping, thereby accelerating AI hardware development.