[8a-N324-1~11] 13.4 Si processing /Si based thin film / MEMS / Equipment technology | The 86th JSAP Autumn Meeting 2025

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Oral presentation13 Semiconductors : 13.4 Si processing /Si based thin film / MEMS / Equipment technology

[8a-N324-1~11]13.4 Si processing /Si based thin film / MEMS / Equipment technology

Mon. Sep 8, 2025 9:00 AM - 12:00 PM JST
Mon. Sep 8, 2025 12:00 AM - 3:00 AM UTC

N324 (Lecture Hall North)

9:00 AM - 9:15 AM JST(12:00 AM - 12:15 AM UTC)

[8a-N324-1]Formation of TiO₂ Films Using Minimal Fab Reactive Sputtering Tool

〇Shuichi Noda¹, Yuuki Yabuta², Naoko Yamamoto², Kamei Ryuichiro², Noriko Miura¹, Shinichi Ikeda¹, Shiro Hara^1,3 (1.AIST, 2.Seinan-kogyo, 3.Hundred Semiconductors)

9:15 AM - 9:30 AM JST(12:15 AM - 12:30 AM UTC)

[8a-N324-2]Development and Contact Resistance Evaluation of Two-Layer Al Interconnection for AIHardware using Minimal Fab

〇Hirofumi Sumi¹, Naonobu Shimamoto¹, Yukinori Ochiai¹, Tohru Mogami¹, Yoshio Mita¹, Makoto Ikeda¹ (1.The Univ. of Tokyo, Systems design lab.)

9:30 AM - 9:45 AM JST(12:30 AM - 12:45 AM UTC)

[8a-N324-3]Development of Isolation Technology for SOI-CMOS Devices in Minimal-Fab Process

〇Hiroshige Kogayu¹, Ryuhei Sekifuji¹, Hiroyuki Tanaka², Noriko Miura², Shiro Hara^1,2 (1.Hundred, 2.AIST)

9:45 AM - 10:00 AM JST(12:45 AM - 1:00 AM UTC)

[8a-N324-4]Analysis of wafer in-plane variation factors in Minimal Fab 2

〇Hiroyoshi Hongoh¹, Shuichi Noda¹, Noriko Miura¹, Shinichi Ikeda¹, Shiro Hara^1,2 (1.AIST, 2.Hundred)

10:00 AM - 10:15 AM JST(1:00 AM - 1:15 AM UTC)

[8a-N324-5]Fabrication of TSVs using Minimal Fab system and evaluation of I/V

〇Takuro Kono¹, Ryuhei Sekifuji², Fumito Imura², Hiroyuki Tanaka³, Noriko Miura³, Shiro Hara³, Toru Aonishi⁴, Ichiro Akai⁵, Yasuo Terasawa¹, Takeshi Hashishin⁵ (1.NIDEK Co., LTD., 2.Hundred Semiconductors Inc., 3.AIST, 4.Tokyo Univ., 5.Kumamoto Univ.)

10:30 AM - 10:45 AM JST(1:30 AM - 1:45 AM UTC)

[8a-N324-6]Study of wafer thinning process using Minimal Fab

〇Hiroyuki Tanaka¹, Hiroshi Tokunaga², Yoshiyuki Nozawa³, Toshihiro Hayami³, Hiroshi Sugiyama⁴, Noriko Miura¹, Shinichi Ikeda¹, Shiro Hara^1,4 (1.AIST, 2.MTC, 3.SPPT, 4.HS)

10:45 AM - 11:00 AM JST(1:45 AM - 2:00 AM UTC)

[8a-N324-7]Process development method for shrinking CMOS devices in Minimal Fab

〇Noriko Miura¹, Hiroshige Kogayu², Shinichi Ikeda¹, Shiro Hara^1,2 (1.AIST, 2.Hundred)

11:00 AM - 11:15 AM JST(2:00 AM - 2:15 AM UTC)

[8a-N324-8]Development strategy for new materials in Minimal Fab

〇Noriko Miura¹, Kazumasa Nemoto¹, Shuichi Noda¹, Shinichi Ikeda¹, Shiro Hara^1,2 (1.AIST, 2.Hundred)

11:15 AM - 11:30 AM JST(2:15 AM - 2:30 AM UTC)

[8a-N324-9]Ultra Energy-saving for electronic chips by FusionCore technology

〇Shiro Hara^1,2, Noriko Miura¹, Shinichi Ikeda¹, Fumito Imura² (1.AIST, 2.Hundred)

11:30 AM - 11:45 AM JST(2:30 AM - 2:45 AM UTC)

[8a-N324-10]Applying Chiplet Technology to Low-Volume Wide-Variety Production: Development of the FusionCore Interconnect Technology

〇Fumito Imura¹, Hiroshi Sugiyama¹, Noriko Miura², Shinichi Ikeda², Shiro Hara^1,2 (1.Hundred, 2.AIST)

11:45 AM - 12:00 PM JST(2:45 AM - 3:00 AM UTC)

[8a-N324-11]Controlling humidity and pressure in a process chamber in wafer droplet cleaning technology

〇Kazumasa Nemoto¹, Noriko Miura¹, Shinichi Ikeda¹, Shiro Hara^1,2 (1.AIST, 2.Hundred)

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