[10p-E218-1~13] 13.4 Si processing /Si based thin film / MEMS / Equipment technology

2:30 PM - 2:45 PM JST(5:30 AM - 5:45 AM UTC)

[10p-E218-5] Optimization of Deep Via-Hole Etching Profiles in Minimal Fab Using the Taguchi L18 Orthogonal Array

〇Hiroyuki Tanaka¹, Yoshiyuki Nozawa², Fumito Imura³, Noriko Miura¹, Shinichi Ikeda¹, Shiro Hara^1,3 (1.AIST, 2.SPPT, 3.HS)

Keywords:

TSV,Quality Engineering,Parameters

TSV deep etching is crucial for 3D Stacking and Chiplet technology, and it has been found that scallop within TSV holes significantly contributes to improving electrical insulation performance. Therefore, we intentionally added noise using the L18 Quality Engineering method to optimize the process. These noises require parameter design with minimal interaction between them. In this study, we found it easier to find optimal values by designing parameters with minimal interaction. On the day of the presentation, we will report on the results of this analysis and the validity of the model.