[10p-S1-1~20] 13.5 Semiconductor devices/ Interconnect/ Integration technologies

5:45 PM - 6:00 PM JST(8:45 AM - 9:00 AM UTC)Presentation by Applicant for JSAP Young Scientists Presentation Award

[10p-S1-16] Study of Stress Suppression Using a Negative Thermal Expansion Material Liner for Through-Silicon Vias (TSVs)

〇YIQING XU¹, RUOBO LAN¹, HISASHI KINO¹ (1.Kyushu Univ.)

Keywords:

TSV,Negative Thermal Expansion