Presentation Information
[15a-PB2-15]Quantitative Evaluation of the Impact of Silicon Wafer Defect Levels on 3.3 kV Si-IGBT Characteristics
〇Bozhou Cai1, Keiji Tagami1, Wataru Saito2, Shin-ichi Nishizawa2 (1.Kyushu Univ. IGSES, 2.Kyushu Univ. RIAM)
Keywords:
Si-IGBT,power device
The performance of high-voltage Si-IGBTs is strongly influenced by deep-level defects in silicon wafers, which affect carrier lifetime through trapping and detrapping processes. In this study, the impact of deep-level traps on a 3.3-kV class Si-IGBT was quantitatively evaluated by introducing trap parameters obtained from DLTS measurements into a TCAD device model. Simulation results show that trap parameters from as-grown FZ-Si wafers increase the turn-off energy loss by 2.4% compared with the trap-free case, whereas the impact is significantly reduced after the thermal process due to lower trap concentrations. In addition, increasing the trap concentration was found to worsen the trade-off between turn-off loss and on-state voltage. These results clarify the importance of trap control for optimizing high-voltage Si-IGBT performance.