Presentation Information
[18a-PA2-4]Proposal of a 1T1R Cell Model and Dynamic Gate-Control Circuit for Accelerating AI Training
〇Sho Hamano1, Yusuke Mizobata1, Kensei Kugio1, Rozu Henmi1, Kaito Tabata1, Munehiro Tada1 (1.Keio Univ.)
Keywords:
Resistive Memory,Analog In-Memory Computing,Neuromorphic
As the demand for faster AI training increases, Analog In-Memory Computing is regarded as a promising approach capable of constant-time computation. However, under constant-voltage updates, the number of available weight states is limited. In this presentation, we propose a dynamic gate-control circuit and a 1T1R cell model for its simulation, and show that multi-level weight behavior can emerge even under constant-voltage updates.