[18a-S2_203-1~10] 13.5 Semiconductor devices/ Interconnect/ Integration technologies

11:45 AM - 12:00 PM JST(2:45 AM - 3:00 AM UTC)

[18a-S2_203-10] Design of parallel-processing in-memory neural-network accelerator macro for INT4 inference

〇Yusaku Shiotsu¹, Satoshi Sugahara¹ (1.FIRST, Inst. of Sci. Tokyo)

Keywords:

Neural network accelerator,Processing-in-memory,Energy minimum point operation