[18a-S2_203-1~10] 13.5 Semiconductor devices/ Interconnect/ Integration technologies

11:30 AM - 11:45 AM JST(2:30 AM - 2:45 AM UTC)

[18a-S2_203-9] An energy-efficient parallel-processing in-memory BNN accelerator macro using XNOR-SRAM

Kein Kondo¹, 〇Yusaku Shiotsu¹, Satoshi Sugahara¹ (1.FIRST, Inst. of Sci. Tokyo)

Keywords:

SRAM,Energy minimum point operation,Processing-in-memory