[AS-1] State-of-the-art Chiplet Design Technologies

1:45 PM - 2:10 PM JST(4:45 AM - 5:10 AM UTC)

[AS-1-01] The Cutting Edge of 3D-IC and Chiplet Design: Accelerating Advanced Packaging with Cadence’s Integrated Solutions

〇Toru Makii¹ (1. Cadence Design Systems)

Keywords:

Semiconductor,Chiplet,EDA,Design,Package